(a) Field of the Invention
The present invention relates to a device of driving a display device.
(b) Description of the Related Art
A liquid crystal display (LCD) or an electro luminescence (EL) display includes a plurality of pixels arranged in a matrix. Each pixel includes a switching element selectively transmitting data voltages, and the switching element includes a typical tri-terminal element such as a metal-oxide-silicon (MOS) transistor. The display device further includes a plurality of gate lines and a plurality of data lines connected to the switching elements. Each gate line transmits a gate-on voltage for turning on the switching elements to be activated and each data line transmits the data voltages to the pixels via the activated switching elements.
The display device further includes a gate driver applying the gate-on voltage to the gate lines, a data driver applying the data voltages to the data lines, and a signal controller for controlling the gate driver and the data driver.
The gate driver starts outputting the gate-on voltage in response to a vertical synchronization signal from the signal controller such that all the gate lines are sequentially supplied with the gate-on voltage. A conventional gate driver includes a plurality of shift registers connected to the respective gate lines for the application of the gate-on voltage. A first the shift register starts outputting the gate-on voltage synchronized with a clock signal in response to the vertical synchronization start signal, while the shift registers except for the first shift register starts outputting the gate-on voltage synchronized with the clock signal in response to outputs of the previous shift registers. The termination of the output of the gate-on voltage in each shift register is closely related to the start time of output of a next shift register.
This is now described in detail.
Each shift register of a conventional gate driver includes an input SR latch and an output AND gate.
The SR latch has a set input terminal for receiving a previous gate output (i.e., an output of a previous shift register) and a reset input terminal for receiving a next gate output (i.e., an output of a next the shift register). The AND gate receives an output of the SR latch and a clock signal and it generates and outputs a gate signal.
The output of the SR latch is low in an initial state where both the previous gate output inputted into the set terminal and the next gate output inputted into the reset terminal are low (or “0”). During the low state of the next gate output, when the previous gate output becomes high (or “1”), the output of the SR latch becomes high. During the low state of the next gate output, the output of the SR latch is kept unchanged even though the previous gate output becomes low again. During the low state of the previous gate output, when the next gate output becomes high, the output of the SR latch becomes low from high. As a result, the output of the SR latch maintains high from the turning point of the previous gate output from low to high to the turning point of the next gate output from low to high, while it becomes low for other times.
The AND gate generates a gate output which has a high value when both the output of the SR latch and the clock signal are high. In detail, the gate output becomes high when the clock signal becomes high from low during the high section of the output of the SR latch, and it becomes low when the clock signal becomes low or the output of the SR latch becomes low.
The conventional gate driver experiences so called a latch-up. The output of the SR latch is well-defined when the set input and the reset input is (0, 0), (1, 0), or (0, 1), respectively, but it is not defined when the set input and the reset input is (1, 1), respectively. Accordingly, there is a problem that the shift register fails to perform a normal operation when both the previous gate output and the next gate output are high due to some reasons.
In particular, the display device selectively receives image signals in various modes and the difference in the image signals in the various modes may make such an abnormal operation during the transition of the image modes.
For example, a period of a data enable signal for defining valid data sections becomes short, or the data enable signal behaves like a valid data section for an invalid data section or vice versa. For the former case, a sufficient reset time of the shift register may not be given, and for the latter case, two of more vertical synchronization start signals are generated or the duration of the vertical synchronization start signal is elongated. These may result in simultaneous output of the gate-on voltage by two or more shift registers. Accordingly, the display device may display an abnormal image, a switch for switching a clock signal and a switch for switching the gate-off voltage may be simultaneously turned on to make short circuit, and signal lines or power supplying lines provided on the display panel may be overloaded to be disconnected.